For example, in order to ensure safety in operation of a power switching element such as a power MOSFET (metal-oxide semiconductor field-effect transistor) and the like, it is required to drive and control the power switching element so that the power switching element is normally-off. A SiC-JFET (silicon carbide junction field effect transistor) and a GaN-FET (gallium nitride field effect transistor) are next generation devices having a remarkably lower loss than Si-MOSFET, and can achieve normally-off. However, it often happens that voltage of only a few V (e.g., about 2 to 3 V) can be applied to gates of these FETs, while the voltage of 10 to 20 V can be applied to a gate of the Si power MOSFET. The devices such as SiC-JFET and GaN-FET cannot be driven at a high voltage, and as a result, high speed switching is difficult.
Patent document 1 (JP-3655049B2 corresponding to U.S. Pat. No. 6,180,959B2) describes a technique for limiting a gate voltage (see FIG. 11 for example). Specifically, a series circuit of a gate resistor and a Zener diode is connected between an emitter of a gate driving transistor and a ground, and a gate of a static induction transistor is connected to a common connection point of the gate resistor and the Zener diode, whereby Zener voltage clamps the gaze voltage.
According to a configuration of Patent Document 1, however, since a current continues to flow through the Zener diode while the static induction transistor is in ON, a loss in the drive circuit is large. The configuration of Patent Document 1 cannot deal with switching in a high frequency band.